UNTAPPED PASSIVE DELAY LINES

WS-XXXX

Wee SIP Untapped Passive Delay Line

- Analog input and output
- Delays stable and precise
- 3-pin Wee SIP package (.180 high)
- Available in delays from 1 ns to 250ns
- Precise, fixed delay
- Available in impedances of 50, 100, 200, 350 and 500 ohms

DESIGN NOTES

The "Wee SIP Series" Lumped Constant Passive Delay Lines developed by Engineered Components Company have been designed to provide precise delays for analog delay line applications. These delay lines provide excellent delay accuracy, low DCR, low attenuation and low distortion.

These delay lines are offered in 188 models with delays from 1 to 250ns. Delay time is measured at the 50% point on the leading edge. Accuracies are maintained as shown under "Operating Characteristics." Temperature coefficient of delay is less than 75 ppm/°C over the operating temperature range of -55 to ±125°C.

The "Wee SIP Series" LC delay lines are intended for use in most analog applications; they are also compatible with the low signal levels of TTL and ECL. These delay lines find extensive use in providing the required delay timing functions necessary in radar, computer, communication, testing and instrument applications.

Construction of the "Wee SIP Series" utilizes miniature inductors and monolithic ceramic capacitors to provide the utmost in miniaturization and reliability. The MTBF on these delay lines, when calculated per MIL-HDBK-217, for a 50°C ground fixed environment and with 5V DC applied, is in excess of 12 million hours.

The "Wee SIP Series" delay lines are packaged in a 3-pin SIP housing, molded of flameproof Diallyl Phthalate per ASTM D 5948, Type SDG-F. These delay lines are designed to meet the applicable portions of MIL-D-23859, and they are capable of meeting the environmental requirements of MIL-STD-202 for moisture resistance, vibration, temperature cycling, humidity and life. Flat metal leads meet the solderability requirements of MIL-STD-202, Method 208. Corner standoffs on the housing provide positive standoff from the printed circuit board to permit solder-fillet formation and flush cleaning of solder-flux residues for improved reliability.

Marking consists of manufacturer's logo (EC²), part number, terminal identification and date code of manufacture. All marking is applied by silk screen process using white epoxy paint in accordance with MIL-STD-130, to meet the permanency of identification required by MIL-STD-202, Method 215.

TEST CONDITIONS

1. All measurements are made at 25°C.
2. Test procedures in accordance with MIL-D-23859.

OPERATING CHARACTERISTICS

Total delay tolerance: ............. See tabulations
Rise time, maximum: ................ See tabulations
Impedance: ......................... 50, 100, 200,
                                     350, or 500 ohms
Impedance tolerance: ............... ±10% 
DC resistance, maximum: ............ See tabulations
Attenuation, maximum: .............. 0.5 db
Distortion, maximum: ............... ±5%
Overshoot, maximum: ................ 10%
Working voltage, maximum: .......... 25V DC
Dielectric strength: ............... 100V DC @ 50uA
Insulation resistance, minimum: .... 10,000 megohms 
                                     @ 100V DC

PART NUMBER TABLE

Special delay lines can be readily manufactured with longer or specific delays, impedances, rise times and package configurations for specific applications.