PROGRAMMABLE PASSIVE DELAY LINES

PADL-1-XX

3-Bit Programmable Analog Delay Line

- Analog input and outputs
- All delays digitally programmable
- Delays stable and precise
- 14-pin DIP package (.240 high)
- Available in delays up to 36ns
- Available in 10 delay steps with resolution from .5 to 5ns

DESIGN NOTES

The "DIP Series" of Programmable Analog Delay Lines developed by Engineered Components Company have been designed to allow for final delay adjustment during or after installation in a circuit. These Programmable Analog Delay Lines incorporate required control circuitry to pick-off analog signals, and are contained in a 14-pin DIP package. These modules are of hybrid construction utilizing the proven technologies of active integrated circuitry and of passive networks utilizing capacitive, inductive and resistive elements. The MTBF on these modules, when calculated per MIL-HDBK-217 for a 500C ground fixed environment, is in excess of 1.6 million hours. The design includes internal termination; no additional external components are needed to obtain the required delay.

These Programmable Analog Delay Lines are digitally programmable by the presence of either a T²L "l " or a "0" at each of the programming pins. Since the input and the output terminals are fixed and the programming is accomplished only by DC voltage levels, programming may be accomplished by remote switching or permanent termination of the appropriate programming pins; the Delay Line may also be programmed automatically by computer generated data. MUX setup time is 24ns typical.

The PADL is offered in 10 models with time delays to a maximum of 36ns and with step resolution as shown in the Part Number Table. Programming of maximum delays is accomplished in 8 delay steps in accordance with the Truth Table examples. Tolerances on minimum delay, delay change per step and deviation from programmed delay are shown in the Part Number Table.

Delay time is measured at the 0 volt level on the leading edge. Temperature coefficient of delay is less than 100 ppm/°C over the operating temperature range of -40 to +85°C.

The PADL is designed for use with analog input signals between -5 and +5 volts and will reproduce them at the output without inversion. Input impedance is 100 ±10 ohms. Output impedance is 170 ohms typical. The -3dB bandwidth is given in the Part Number Table. In general, shorter delays will correspond to increased line bandwidth.

These "DIP Series" Programmable Analog Delay Lines are packaged in a 14-pin DIP housing, molded of flameproof Diallyl Phthalate per ASTM D 5948, Type SDG-F and are fully encapsulated in epoxy resin. Leads meet the solderability requirements of MIL-STD-202, Method 208. Corner standoffs on the housing provide positive standoff from the printed circuit board to permit solder-fillet formation and flush cleaning of solder-flux residues for improved reliability.

Marking consists of manufacturer's name, logo (EC²), part number, terminal identification and date code of manufacture. All marking is applied by silk screen process using white epoxy paint in accordance with MIL-STD-130, to meet the permanency of identification required by MIL-STD-202, Method 215.

TEST CONDITIONS

1. All measurements are made at 25°C.
2. Vcc supply voltage is maintained at 5.0V DC.
3. Vee supply voltage is maintained at -5.0V DC.
4. All units are tested with a I0 Mhz sine wave.
5. Output is loaded with 100K ohms to ground.

OPERATING SPECIFICATIONS

* Vcc supply voltage: ............... 4.75 to 5.25V DC 
* Vee supply voltage: ............... -2.0 to -5.25V DC
Vee to Vcc voltage: ................. 10.0V DC max.
Supply current: ..................... <1 ma typical

Input impedance: .................... 100 ohms ±10% 

Programming and enable pins:
     Low level input voltage ........ 2.0V min.
     High level input voltage: ...... 0.8V max.
     Input leakage current .......... 1 uA max.

Operating temperature range: ........ -40 to +85°C.
Storage temperature: ................ -55 to +125°C.

*For proper operation of the delay line, analog input voltages should not exceed the Vee or Vcc supplies.

PART NUMBER TABLE

ø DELAYS AND TOLERANCES (in ns)

	3      0 2      0 1      0	0 0 1	0  1 0	0 1 1	1  0  0	1 0 1	1 1  0	1 1 1
PADL-1-0.5	1	.5	1	1.5	2	2.5	3	3.5
PADL-1-1.0	1	1	2	3	4	5	6	7
PADL-1-1.5	1	1.5	3	4.5	6	7.5	9	10.5
ETC.

* Delay at step zero is referenced to the input pin.
**All delay times after step zero are referenced to step zero.

ø Special modules can be readily manufactured to improve accuracies and/or provide customer specified delay times for specific applications.