PROGRAMMABLE LOGIC DELAY LINES

PECLDL-8-XX

6-Bit Programmable 10K ECL Logic Delay Line

- ECL input and output levels
- Delays stable and precise
- 48-pin DIP package (.250 high)
- Available in delays up to 323ns
- Available in 5 delay steps with resolution from 1 to 5ns
- Propagation delays fully compensated
- All delays digitally programmable
- 70 ECL DC fan-out capacity

DESIGN NOTES

The "DIP Series" of Programmable Logic Delay Lines developed by Engineered Components Company have been designed to allow for final delay adjustment during or after installation in a circuit. These Logic Delay Lines incorporate required driving and pick-off circuitry and are contained in a 48-pin DIP package compatible with ECL "10,000 Series" circuits. The design includes compensation for propagation delays and incorporates internal termination at the output; no additional external components are needed to obtain the required delay.

The Logic Delay Lines are digitally programmable by the presence of either a "1" or a "0" at each of the programming pins. Since the input and the output terminals are fixed and the programming is accomplished only by DC voltage levels, programming may be accomplished by remote switching or permanent termination of the appropriate programming pins of the Logic Delay Line to Vcc; the Logic Delay Line may also be programmed automatically by computer generated data. MUX set-up time is 2ns typical.

The PECLDL is designed for use with positive input pulses and will reproduce these at the output without inversion. Input is a standard ECL 10,000 series single fan-in. All modules can be driven from a standard ECL gate with an external pulldown resistor of 100 ohms to -2V or 470 ohms to -5.2V. Output is standard ECL 10,000 open emitter; programming inputs are standard ECL 10,000 single fan-in. These Logic Delay Lines have the capability of driving up to 70 ECL DC loads.

The PECLDL is offered in 5 models with time delays to a maximum of 323ns and with step resolution as shown in the Part Number Table. Programming of maximum delays is accomplished in 64 delay steps in accordance with the Truth Table examples. Tolerances on minimum delay, delay change per step and deviation from programmed delay are shown in the Part Number Table.

Rise time for all Logic Delay Lines is 5ns maximum, when measured from 20% to 80% pulse amplitude. Temperature coefficient of delay is less than 150 ppm/°C over the operating temperature range of -30° to +85°C.

These modules are of hybrid construction utilizing the proven technologies of active integrated circuitry and of passive networks utilizing capacitive, inductive and resistive elements. The ICs utilized in these modules are burned-in to Level B of MIL-STD-883 to ensure a high MTBF. The MTBF on these modules, when calculated per MIL-HDBK-217 for a 50°C ground fixed environment, is in excess of 500,000 hours.

The "DIP Series" Programmable Logic Delay Lines are packaged in a 48-pin DIP housing, molded of flame-proof Diallyl Phthalate per ASTM D 5948, Type SDG-F, and are fully encapsulated in epoxy resin. Flat metal leads meet the solderability requirements of MIL-STD-202, Method 208. Leads provide positive standoff from the printed circuit board to permit solder-fillet formation and flush cleaning of solder-flux residues for improved reliability.

Marking consists of manufacturer's name, logo (EC²), part number, terminal identification and date code of manufacture. All marking is applied by silk screen process using white epoxy paint in accordance with MIL-STD-130, to meet the permanency of identification required by MIL-STD-202, Method 215.

TEST CONDITIONS

1. All measurements are made at 25°C.
2. Vee supply voltage is maintained at -5.2V DC.
3. All units are tested using a positive input pulse provided by a standard open emitter ECL 10,000 gate. The input and output utilize a 100 ohm pulldown resistor to -2V; the output is also loaded with one ECL 10,000 gate.
4. Input pulse width used is 100ns; Pulse period for all units is 5000ns.

OPERATING SPECIFICATIONS

Supply Voltage: ............... -5.2V ±5% to Vee 
                  (Can be operated on +5V to Vcc)
Supply Current: ............... 165mA typical
Logic 1 Input at 25°C.
   Voltage .................... -.98V min.
   Current .................... 265uA max.
Logic 0 Input at 25°C.
   Voltage .................... -1.63V max.
   Current .................... 0.5uA min.
Logic 1 Output at 25°C ......... -.96V min.
Logic 0 Output at 25°C ......... -1.65 5V max.
Operating temperature range: ... -30° to +85°C.
Storage temperature range: ..... -55° to +125°C.

PART NUMBER TABLE

ø DELAYS AND TOLERANCES (in ns)

TRUTH TABLE EXAMPLES

	6      0 5      0 4      0 3      0 2      0 1      0	0  0 0 0 0 1	0  0 0 0 1 0	0  0 0 0 1 1	0  0 0 1 0 0	0  0 0 1 0 1	0  0 0 1 1 0	0  0 0 1 1 1	0  0 1 0 0 0	0  0 1 0 0 1	0  0 1 0 1 0	0  0 1 0 1 1	0  0 1 1 0 0	0  0 1 1 0 1	...	1 1 1 1 1 0	1 1 1 1 1 1
PECLDL-8-1	8	1	2	3	4	5	6	7	8	9	10	11	12	13	...	62	63
PECLDL-8-2	8	2	4	6	8	10	12	14	16	18	20	22	24	26	...	124	126
PECLDL-8-3	8	3	6	9	12	15	18	21	24	27	30	33	36	39	...	186	189
PECLDL-8-4	8	4	8	12	16	20	24	28	32	36	40	44	48	52	...	248	252
PECLDL-8-5	8	5	10	15	20	25	30	35	40	45	50	55	60	65	...	310	315

* Delay at step zero is referenced to the input pin.
** All delay times after step zero are referenced to step zero.

ø All modules can be operated with a minimum input pulse width of 25% of full delay and pulse period approaching square wave; since delay accuracies may be somewhat degraded, it is suggested that the module be evaluated under the intended specific operating conditions.

Special modules can be readily manufactured to improve accuracies and/or provide customer specified delay times for specific applications.