PROGRAMMABLE LOGIC DELAY LINES

PDL-ACT-8-XX

3-Bit Programmable ACT Logic Delay Line

- T²L compatible input and output
- Standby power 5 nano watts max.
- Delays stable and precise
- 16-pin DIP package (.240 high)
- Available in delays up to 358ns
- Available in 22 delay steps with resolution from 1 to 50ns
- Propagation delays fully compensated
- All delays digitally programmable
- 10 T²L fan-out capacity

DESIGN NOTES

The "DIP Series" of Programmable Logic Delay Lines developed by Engineered Components Company have been designed to allow for final delay adjustment during or after installation in a circuit. These Logic Delay Lines incorporate required driving and pick-off circuitry and are contained in a 16-pin DIP package compatible with T²L, Advanced CMOS and Fast circuits. These modules are of hybrid construction utilizing the proven technologies of active integrated circuitry and of passive networks utilizing capacitive, inductive and resistive elements. The ICs utilized in these modules are burned-in to Level B of MIL-STD-883 to ensure a high MTBF. The MTBF on these modules, when calculated per MIL-HDBK-217 for a 50°C ground fixed environment, is in excess of 1.5 million hours. The design includes compensation for propagation delays and incorporates internal termination at the output.No additional external components are needed to obtain the required delay.

The Logic Delay Lines are digitally programmable by the presence of either a "1" or a "0" at each of the programming pins. Since the input and output terminals are fixed and the programming is accomplished only by DC voltage levels, programming may be accomplished by remote switching or permanent termination of the appropriate programming pins to logic "1" or "0" levels; the Logic Delay Line may also be programmed automatically by computer generated data. MUX set-up time is 3ns typical.

The PDL-ACT is offered in 22 models with time delays to a maximum of 358ns and with step resolution as shown in the Part Number Table. Programming of maximum delay is accomplished in 8 steps in accordance with the Truth Table examples. Tolerances on minimum delay, delay change per step and deviation from the programmed delay are shown in the Part Number Table.

Delay time is measured at the +1.5V level on the leading edge. Rise time is measured from 0.75V to 2.4V. With a 50pf load, maximum rise time is 1.5ns. Temperature coefficient of delay is approximately +350 ppm/°C over the operating temperature range of 40 to +85°C.

The PDL-ACT is designed for use with positive input pulses and will reproduce these at the output without inversion; an inverted output is also provided simultaneously at OUT. Output is advanced CMOS logic; programming pins are Advanced CMOS single fan-in. These Logic Delay Lines have the capability of driving up to 10 T²L loads.

These "DIP Series" Programmable Logic Delay Lines are packaged in a 16-pin DIP housing, molded of flame-proof Diallyl Phthalate per ASTM D 5948, type SDG-F, and are fully encapsulated in epoxy resin. Leads meet the solderability requirements of MIL-STD-202, Method 208. Corner standoffs on the housing provide provide positive standoff from the printed circuit board to permit solder-fillet formation and flush cleaning of solder-flux residues for improved reliability.

Marking consists of manufacturer's name, logo (EC²), part number, terminal identification and date code of manufacture. All marking is applied by silk screen process using white epoxy paint in accordance with MIL-STD-130, to meet the permanency of identification required by MIL-STD-202, Method 215.

TEST CONDITIONS

1. All measurements are made at 25°C.
2. Vcc supply voltage is maintained at 5.0V DC.
3. All units are tested using a ACT toggle-type positive input pulse and one ACT load at the output.
4. Input pulse width used is 600ns. Pulse period for all units is 5,000ns.

OPERATING SPECIFICATIONS

* Vcc supply voltage: .......... 4.75 to 5.25V DC
Vcc supply current:
   Constant "1" or "0" in ...... 1na typical
   Constant 1 Mhz square wave .. 10ma typical
Logic 1 input:
     Voltage ................... 2V min.; Vcc max. 
Logic 0 input:
     Voltage ................... 0.8V max. 
Logic 1 Voltage out: ........... 4.3V min. @ -24ma 
Logic 0 Voltage out: ........... 0.44 max. @ +24ma 
Operating temperature range: ... -40 to +85°C. 
Storage temperature: ........... -55 to +125°C.

* Delays increase approximately 2% for an increase or decrease of 5% in supply voltage.

PART NUMBER TABLE

ø DELAYS AND TOLERANCES (in ns)

TRUTH TABLE EXAMPLES

	3    0 2    0 1    0	0  0 1	0  1 0	0  1 1	1  0  0	1  0  1	1 1 0	1 1 1
PDL-ACT-8-1	8	1	2	3	4	5	6	7
PDL-ACT-8-2	8	2	4	6	8	10	12	14
PDL-ACT-8-3	8	3	6	9	12	15	18	21
ETC.

*Delay at step zero is referenced to the input pin.
**All delay times after step zero are referenced to step zero.

ø All modules can be operated with a minimum input pulse width of 40% of full delay and pulse period approaching square wave; since delay accuracies may be somewhat degraded, it is suggested that the module be evaluated under the intended specific operating conditions.

Special modules can be readily manufactured to improve accuracies and/or provide customer specified delay times for specific applications.