PROGRAMMABLE LOGIC DELAY LINES

BPECLDL-4.5-XX / DPECLDL-4.5-XX

8-Bit Binary/Decade Programmable 100K ECL Logic Delay Line

- ECL input and output levels
- Delays stable and precise
- 34-pin DIP package (.375 high)
- Available in delays up to 132ns
- Available in Binary and Decaded versions
- Step resolution from 0.1 to 0.5ns
- Propagation delays fully compensated
- All delays digitally programmable
- 70 ECL DC fan-out capacity

DESIGN NOTES

The "DIP Series" of Programmable Logic Delay Lines developed by Engineered Components Company have been designed to allow for final delay adjustment during or after installation in a circuit. These Logic Delay Lines incorporate required driving and pick-off circuitry and are contained in a 34-pin DIP package compatible with ECL "100K Series" circuits. The design includes compensation for propagation delays and incorporates internal termination at the output; no additional external components are needed to obtain the required delay.

The Logic Delay Lines are digitally programmable by the presence of either a "1" or a "0" at each of the programming pins. Since the input and the output terminals are fixed and the programming is accomplished only by DC voltage levels, programming may be accomplished by remote switching or permanent termination of the appropriate programming pins of the Logic Delay Line to Vcc; the Logic Delay Line may also be programmed automatically by computer generated data. MUX set-up time is 1ns maximum. When no need exists in the application to change delay time during normal use, the desired delay is most conveniently established by use of a Vcc pad around each programming pin; programming is accomplished by cutting off those pins which are to remain at state "0" before insertion of the Logic Delay Line into the printed circuit board.

The BPECLDL and the DPECLDL are designed for use with positive input pulses and will reproduce these at the output without inversion. Input is a standard ECL 10,000 series single fan-in. All modules can be driven from a standard ECL gate with an external pulldown resistor of 50 ohms or 100 ohms to -2V or 470 ohms to -4.5V. Output is standard ECL 100K open emitter; programming inputs are standard ECL 100K single fan-in. These Logic Delay Lines have the capability of driving up to 70 ECL DC loads.

These modules are offered in Binary and Decade models with time delays to a maximum of 132ns and with step resolution as shown in the Part Number Table. Programming of maximum delays is accomplished in 256 delay steps in accordance with the Truth Table examples. Tolerances on minimum delay, delay change per step and deviation from programmed delay are shown in the Part Number Table.

Rise time for all Logic Delay Lines is 2ns maximum, when measured from 20% to 80% pulse amplitude. Temperature coefficient of delay is less than 150 ppm/°C over the operating temperature range of 0 to +85°C.

These modules are of hybrid construction utilizing the proven technologies of active integrated circuitry and of passive networks utilizing capacitive, inductive and resistive elements. The ICs utilized in these modules are burned-in to Level B of MIL-STD-883 to ensure a high MTBF. The MTBF on these modules, when calculated per MIL-HDBK-217 for a 50°C ground fixed environment, is in excess of 500,000 hours.

The "DIP Series" Programmable Logic Delay Lines are packaged in a 34-pin DIP housing, molded of flame-proof Diallyl Phthalate per ASTM D 5948, Type SDG-F, and are fully encapsulated in epoxy resin. Leads meet the solderability requirements of MIL-STD-202, Method 208. Corner standoffs on the housing provide positive standoff from the printed circuit board Leads provide positive standoff from the printed circuit board to permit solder-fillet formation and flush cleaning of solder-flux residues for improved reliability.

Marking consists of manufacturer's name, logo (EC²), part number, terminal identification and date code of manufacture. All marking is applied by silk screen process using white epoxy paint in accordance with MIL-STD-130, to meet the permanency of identification required by MIL-STD-202, Method 215.

TEST CONDITIONS

1. All measurements are made at 25°C.
2. Vee supply voltage is maintained at -4.5V DC.
3. All units are tested using a positive input pulse provided by a standard open emitter ECL 100K gate. The input and output utilize a 50 ohm pulldown resistor to -2V; the output is also loaded with one ECL 100K gate.
4. Input pulse width used is 100ns. Pulse period for all units is 1000ns.

OPERATING SPECIFICATIONS

Supply Voltage: ................ -4.2V to -4.8 Vee 
Supply Current: ................ 200ma typical

Logic 1 Input at 25°C.
   Voltage ..................... -1.165V min.
   Current 350ua max.
Logic 0 Input at 25°C.
   Voltage ..................... -1.475V max.
   Current ..................... 0.5ua min.
Logic 1 Output at 25°C ......... -1.025V min.
Logic 0 Output at 25°C. ........ -1.620V max.
Operating temperature range: ... 0° to +85°C.
Storage temperature range: ..... -55° to +125°C

PART NUMBER TABLE

BINARY ø DELAYS AND TOLERANCES (in ns)

TRUTH TABLE EXAMPLES

	8        0 7        0 6        0 5        0 4        0 3        0 2        0 1        0	0 0 0 0 0 0 0 1	0 0 0 0 0 0 1 0	0 0 0 0 0 0 1 1	0 0 0 0 0 1 0 0	0 0 0 0 0 1 0 1	0 0 0 0 0 1 1 0	0 0 0 0 0 1 1 1	0 0 0 0 1 0 0 0	0 0 0 0 1 0 0 1	0 0 0 0 1 0 1 0	0 0 0 0 1 0 1 1	0 0 0 0 1 1 0 0	0 0 0 0 1 1 0 1	...	1 1 1 1 1 1 1 0	1 1 1 1 1 1 1 1
BPECLDL-4.5-0.1	4.5	0.1	0.2	0.3	0.4	0.5	0.6	0.7	0.8	0.9	1.0	1.1	1.2	1.3	...	25.4	25.5
BPECLDL-4.5-0.2	4.5	0.2	0.4	0.6	0.8	1.0	1.2	1.4	1.6	1.8	2.0	2.2	2.4	2.6	...	50.8	51.0
BPECLDL-4.5-0.3	4.5	0.3	0.6	0.9	1.2	1.5	1.8	2.1	2.4	2.7	3.0	3.3	3.6	3.9	...	76.2	76.5
BPECLDL-4.5-0.4	4.5	0.4	0.8	1.2	1.6	2.0	2.4	2.8	3.2	3.6	4.0	4.4	4.8	5.2	...	101.6	102.0
BPECLDL-4.5-0.5	4.5	0.5	1.0	1.5	2.0	2.5	3.0	3.5	4.0	4.5	5.0	5.5	6.0	6.5	...	127.0	127.5

PART NUMBER TABLE

DECADE ø DELAYS AND TOLERANCES (in ns)

TRUTH TABLE EXAMPLES

	8        0 7        0 6        0 5        0 4        0 3        0 2        0 1        0	0 0 0 0 0 0 0 1	0 0 0 0 0 0 1 0	0 0 0 0 0 0 1 1	0 0 0 0 0 1 0 0	0 0 0 0 0 1 0 1	0 0 0 0 0 1 1 0	0 0 0 0 0 1 1 1	0 0 0 0 1 0 0 0	0 0 0 0 1 0 0 1	0 0 0 0 1 0 1 0	0 0 0 0 1 0 1 1	0 0 0 0 1 1 0 0	0 0 0 0 1 1 0 1	...	1 0 0 1 1 0 0 0	1 0 0 1 1 0 0 1
DPECLDL-4.5-0.1	4.5	0.1	0.2	0.3	0.4	0.5	0.6	0.7	0.8	0.9	1.0	1.1	1.2	1.3	...	9.8	9.9
DPECLDL-4.5-0.2	4.5	0.2	0.4	0.6	0.8	1.0	1.2	1.4	1.6	1.8	2.0	2.2	2.4	2.6	...	19.6	19.8
DPECLDL-4.5-0.3	4.5	0.3	0.6	0.9	1.2	1.5	1.8	2.1	2.4	2.7	3.0	3.3	3.6	3.9	...	76.2	76.5
DPECLDL-4.5-0.4	4.5	0.4	0.8	1.2	1.6	2.0	2.4	2.8	3.2	3.6	4.0	4.4	4.8	5.2	...	101.6	102.0
DPECLDL-4.5-0.5	4.5	0.5	1.0	1.5	2.0	2.5	3.0	3.5	4.0	4.5	5.0	5.5	6.0	6.5	...	127.0	127.5

* Delay at step zero is referenced to the input pin
** All delay times after step zero are referenced to step zero.

ø All modules can be operated with a minimum input pulse width of 20% of full delay, whichever is greater, and pulse period approaching square wave; since delay accuracies may be somewhat degraded, it is suggested that the module be evaluated under the intended specific operating conditions.

Special modules can be readily manufactured to improve accuracies and/or provide customer specified delay times for specific applications.