MULTIPLE LOGIC DELAY LINES

MECLDL-XX

Multi 10K ECL Logic Delay Line

- ECL inputs and outputs
- Delays stable and precise
- 16-pin DIP package (.250 high)
- Available in delays from 5 to l00ns -- each isolated and with 70 ECL DC fan-out capacity
- Fast rise time on all outputs

DESIGN NOTES

The "DIP Series" Multiple Logic Delay Lines developed by Engineered Components Company have been designed to provide precise delays with required driving and pick-off circuitry contained in a single 16-pin DIP package compatible with ECL "10,000 Series" circuits. These logic delay lines are of hybrid construction utilizing the proven technologies of active integrated circuitry and of passive networks utilizing capacitive, inductive and resistive elements. The ICs utilized in these modules are burned-in to Level B of MIL-STD-883 to ensure a high MTBF. The MTBF on these modules, when calculated per MIL-HDBK-217B for a 50°C ground fixed environment, is in excess of 1.5 million hours. Module design includes compensation for propagation delays and incorporates internal termination at the output; no additional external components are needed to obtain the desired delay.

The MECLDL is offered in 36 delays from 5 to l00ns. Delay tolerances and rise times are maintained as shown in the accompanying Part Number Table, when tested under the "Test Conditions" shown. Delay time is measured at the -1.3V level on the leading edge; rise time is measured from 20% to 80% pulse amplitude. Temperature coefficient of delay is less than ±500 ppm/°C over the operating temperature range of -30 to +85°C.

These modules accept either logic "1" or logic "0" inputs and reproduce the logic at the output without inversion. The delay modules are intended primarily for use with positive going pulses and are calibrated to the tolerances shown in the table on rising edge delay; where best accuracy is desired in applications using failing edge timing, it is recommended that a special unit be calibrated for the specific application. Each module has the capability of driving up to 70 ECL DC loads.

These "DIP Series" modules are packaged in a 16-pin DIP housing, molded of flame-proof Diallyl Phthalate per ASTM D 5948, Type SDG-F, and are fully encapsulated in epoxy resin. Flat metal leads meet the solderability requirements of MIL-STD-202, Method 208. Leads provide positive standoff from the printed circuit board to permit solder-fillet formation and flush cleaning of solder-flux residues for improved reliability.

Marking consists of manufacturer's name, logo (EC²), part number, terminal identification and date code of manufacture. All marking is applied by silk screen process using white epoxy paint in accordance with MIL-STD-130, to meet the permanency of identification required by MIL-STD-202, Method 215.

TEST CONDITIONS

1. All measurements are made at 25°C.
2. Vee supply voltage is maintained at -5.2V DC.
3. All units are tested using a positive input pulse provided by a standard open emitter ECL 10,000 gate. The input and out put utilize a 100 ohm pulldown resistor to -2V; the output is also loaded with one ECL 10,000 gate.
4. Input pulse width used is 100% longer than delay of module under test; spacing between pulses (failing edge to rising edge) is three times the pulse width used.

OPERATING SPECIFICATIONS

*Supply voltage: ............... -5.2V ±5% to Vee 
                  (can be operated on +5V to Vcc).
Supply current: ................ 90ma typical
Logic 1 input at 25°C:
   Voltage ..................... -.98 min.
   Current ..................... 265ua max.
Logic 0 input at 25°C:
   Voltage ..................... -1.63 max.
   Current ..................... 0.5ua min.
Logic 1 Voltage out at 25°C: ... -.96 min.
Logic 0 Voltage out at 25°C: ... -1.65 max.
Operating temperature range: ... -30 to +85°C
Storage temperature: ........... -55 to +125°C

* Delays increase or decrease less than 1% for a respective increase or decrease of 5% in supply voltage.

PART NUMBER TABLE

ø DELAYS AND TOLERANCES (in ns)

ø All modules can be operated with a minimum input pulse width of 100% of full delay and pulse period approaching square wave; since delay accuracies may be somewhat degraded, it is suggested that the module be evaluated under the intended specific operating conditions.

Special modules can be readily manufactured to improve accuracies and/or provide customer specified random delay times for specific applications.