LOGIC DELAY MODULES

100K-ECL-LDM-XX

8-Tap 100K ECL Logic Delay Module

        - 100K ECL input and outputs
        - Delays stable and precise
        - 24-pin DIP package (.300 high)
        - Available in delays from 9 to 80ns
        - 12.5% taps--each isolated and with 70 ECL DC fan-out capacity
        - Fast rise time on all outputs

DESIGN NOTES

The "DIP Series" Logic Delay Modules developed by Engineered Components Company have been designed to provide precise tapped delays with required driving and pick-off circuitry contained in a 24-pin DIP package compatible with ECL "100K Series" circuits. The design includes compensation for propagation delays and incorporates internal termination at the output; no additional external components are needed to obtain the required delay.

These modules accept either logic "1" or logic "0" inputs and reproduce the logic at the selected output tap without inversion. The delay modules are intended primarily for use with positive going pulses and are calibrated to the tolerances shown in the table on rising edge delay; where best accuracy is desired in applications using failing edge timing, it is recommended that a special unit be calibrated for the specific application. All modules can be driven from a standard ECL gate with an external pulldown resistor of 50 or 100 ohms to -2V or 470 ohms to -4.5V. Output is standard ECL 100K open emitter. Each module has the capability of driving up to 70 ECL DC loads on any one tap.

The 100K ECL LDM is offered in nineteen (19) delays from 9n to 80ns, with each module incorporating taps at 12.5% increments of total delay. Delay tolerances and rise times are maintained as shown in the accompanying Part Number Table, when tested under the "Test Conditions" shown. Delay time is measured at the -1.3V level on the leading edge; rise times are measured from 20% to 80% pulse amplitude. Temperature coefficient of delay is less than 150 ppm/°C over the operating temperature range of 0 to +85°C.

These modules are of hybrid construction utilizing the proven technologies of active integrated circuitry and of passive networks utilizing capacitive, inductive and resistive elements. The ICs utilized in these modules are burned-in to Level B of MIL-STD-883 to ensure a high MTBF. The MTBF on these modules, when calculated per MIL-HDBK-217 for a 50°C ground fixed environment, is in excess of 1 million hours.

These "DIP Series" Logic Delay Modules are packaged in a 24-pin DIP housing, molded of flame-proof Diallyl Phthalate per ASTM D 5948, Type SDG-F, and are fully encapsulated in epoxy resin. Leads meet the solderability requirements of MIL-STD-202, Method 208. Corner standoffs on the housing provide positive standoff from the printed circuit board to permit solder-fillet formation and flush cleaning of solder-flux residues for improved reliability.

Marking consists of manufacturer's name, logo (EC²), part number, terminal identification and date code of manufacture. All marking is applied by silk screen process using white epoxy paint in accordance with MIL-STD-130, to meet the permanency of identification required by MIL-STD-202, Method 215.

TEST CONDITIONS

1. All measurements are made at 25°C.
2. Vee supply voltage is maintained at -4.5V DC
3. All units are tested using a positive input pulse provided by a standard open emitter ECL 100K gate. The input and output utilize a 50 ohm pulldown resistor to -2V; the output being tested is also loaded with one ECL 100K gate.
Æ4. Input pulse width used is 5 to l0ns longer than full delay of module under test; spacing between pulses (falling edge to rising edge) is three times the pulse width used.

OPERATING SPECIFICATIONS

*Supply Voltage:................................. -4.5V ±5% to Vee
Supply Current:.................................. 80ma typical 

Logic 1 Input at 25°C:
     Voltage..................................... -1.165V min.
     Current..................................... 350ua max. 

Logic 0 Input at 25°C:
     Voltage..................................... -1.475V max.
     Current..................................... 0.5ua min. 

Logic 1 Output at 25°C:.......................... -1.025V min.
Logic 0 Output at 25°C:.......................... -1.620V max. 

Operating temperature range:..................... 0 to +85°C.
Storage temperature:............................. -55 to +125°C. 
                      

*Delays increase or decrease less than .5% for an increase or decrease of 5% in supply voltage.

PART NUMBER TABLE

ÆAll modules can be operated with a minimum input pulse width of 25% of full delay and pulse period approaching square wave; since delay accuracies may be somewhat degraded, it is suggested that the module be evaluated under the intended specific operating conditions.

Special modules can be readily manufactured to improve accuracies and/or provide customer specified random delay times for specific applications.